Illustrative embodiments relate to a charge sensing technique, and more particularly to a bitline sense amplifier included in a semiconductor memory device, a memory core including the bitline sense amplifier and a method of sensing charge from a memory cell connected to a bitline.
A semiconductor memory device stores data into a memory cell by performing a write operation, and reads the stored data by performing a read operation. The read operation generally includes a precharge operation followed by a sensing operation. In the precharge operation, a bitline pair is precharged to a predetermined voltage level. After the bitline pair has been precharged, a charge sharing operation is performed, such that charges stored in the memory cell are shared with the bitline pair. A difference between voltage levels of the bitlines in the bitline pair is caused due to the charge sharing operation. In the sensing operation, the voltage difference is sensed and amplified to determine the data stored in the memory cell. For example, the voltage levels of the bitline pair are developed (e.g., decreased or increased) according to the stored data, and then the developed voltage levels of the bitline pair are sensed to determine the data stored in the memory cell. The semiconductor memory device generally includes multiple bitline sense amplifiers that sense and amplify the voltage differences.